Fabricating unique chips using a charged particle multi-beamlet lithography system

ABSTRACT

Method of manufacturing electronic devices using a maskless lithographic exposure system using a maskless pattern writer. The method comprises generating beamlet control data for controlling the maskless pattern writer to expose a wafer for creation of the electronic devices, wherein the beamlet control data is generated based on a feature data set defining features selectable for individualizing the electronic devices, wherein exposure of the wafer according to the beamlet control data results in exposing a pattern having a different selection of the features from the feature data set for different subsets of the electronic devices.

CLAIM FOR PRIORITY

This application is a continuation application of application Ser. No.16/572,592, entitled “FABRICATING UNIQUE CHIPS USING A CHARGED PARTICLEMULTI-BEAMLET LITHOGRAPHY SYSTEM,” filed Sep. 16, 2019, which is acontinuation application of application Ser. No. 15/389,593, entitled“FABRICATING UNIQUE CHIPS USING A CHARGED PARTICLE MULTI-BEAMLETLITHOGRAPHY SYSTEM,” filed Dec. 23, 2016, which claims priority fromU.S. provisional application No. 62/413,470 filed on Oct. 27, 2016. Allabovementioned applications are hereby incorporated by references intheir entireties.

TECHNICAL FIELD

The invention relates to a method of manufacturing, i.e. fabricatingelectronic devices such as semi-conductor chips. More specifically, theinvention relates to the fabrication of unique chips using a chargedparticle multi-beamlet lithography machine, wherein the uniqueness ofthe chips is defined by features included in the chips. Consequently theinvention equally relates to unique chips produced using this new methodof manufacture, as well as to so called “fabs”, i.e. manufacturingfacilities applying this novel method, and to maskless lithographicexposure system adapted for executing the improved method ofmanufacture.

BACKGROUND ART

In the semiconductor industry, lithography systems are used to create,i.e. fabricate such electronic devices, typically in the form ofintegrated circuits formed on silicon wafer, commonly referred to assemiconductor chips. Photolithography utilizes reusable optical masks toproject an image of a pattern representing the desired circuitstructures onto a silicon wafer as part of the manufacturing process.The mask is used repeatedly to image the same circuit structures ondifferent parts of a silicon wafer and on subsequent wafers, resultingin a series of identical chips being fabricated with each wafer, eachchip having an identical circuit design.

In contemporary days, various technologies relating to data security,traceability, and anti-counterfeiting create an increasing need forunique chips having unique circuits or codes, or other unique hardwarefeatures for diversification of the chips. Such unique chips are knownand often implement a security related operation in an obfuscated mannerrequiring the chip to be truly unique. The known unique chips aretypically realized after the manufacture of a chip, e.g. bymanufacturing a series of identical chips using mask based lithographyand then, after manufacture, disrupting certain connections in the chipor by assessing the uniqueness of the chip afterwards upon inspectionand control of certain features. The masks used in this process areexpensive to produce, and manufacturing a unique mask for each singlechip is clearly much too expensive, for which reason mask basedphotolithography is considered unsuitable for fabricating unique chips.

Hence it has been suggested to utilize maskless lithography for thepurpose of creating unique chips. With maskless lithography no mask isused, and instead the required pattern representing the circuit designis input to the maskless lithography system in the form of a data filesuch as a GDSII or OASIS file containing the circuit design layout to betransferred to the target, e.g. wafer, to be exposed by the masklesslithography system.

A maskless lithography and data input system is disclosed in WO2010/134026 in the name of Applicant of the present invention. WO2010/134026 is hereby incorporated by reference in its entirety. Thedisclosed maskless system writes patterns onto wafers directly usingcharged particle beamlets such as electron beamlets. Because the desiredpattern for exposing each chip is represented as data instead of a mask,it becomes possible to utilize such system for the manufacture of uniquechips. The pattern data that is input to the exposure system,representing the unique electronic devices or chips to be created, maybe made unique by using a different GDSII input file for each uniqueelectronic device to be created.

WO 2011/117253 and WO 2011/051301, both assigned to the Applicant of thepresent invention and hereby incorporated by reference in theirentirety, disclose various examples of electronic devices or chips thatcan be created using a charged particle lithography system.

A straight forward method of creating secure, at least unique devices,i.e. using the known maskless exposure system, may however not beoptimized, at least adapted for securely producing unique electronicdevices. Disadvantageously, the processing of GDSII or OASIS filesassociated herewith is typically performed outside of the operations ofthe operator of the lithography system. Moreover, the processedGDSII/OASIS files may be used and stored over a longer period of time.

It is deemed desirable according insight underlying and in fact part ofthe present invention to minimize exposure and exposure time of theunique design data used in the creation of the unique electronic devicesor chips for security reasons, as the uniqueness of the electronicdevice or chip will typically be used for data security, traceabilityand anti-counterfeiting applications.

SUMMARY OF THE INVENTION

The present invention provides a solution for manufacture of uniqueelectronic devices by implementing different features from a set offeatures in different ones of the electronic devices. The electronicdevices may comprise semiconductor chips produced by exposing patternson a semiconductor wafer, and the features may include, for example, oneor more of a circular shaped feature, a feature shaped as a horizontalline, a feature shaped as a vertical line, a feature shaped as a plussign, and combinations thereof, which result in electrical connectionsbeing formed within or between layers of the chip when exposed on thewafer. The features may form a part of or a complete electronic circuitin the electronic device, and the electronic circuit may be adapted forgenerating a certain predetermined output as a response to a certainpredetermined electronic input.

One way of making such electronic devices unique is by selectingdifferent sets of features to be used for making different individualelectronic devices of a set of electronic devices, therebyindividualizing the electronic devices. Such a set of electronic devicesmay be devices which all perform the same function, such as providing apredetermined electronic output as a response to a certain predeterminedelectronic input. Such devices may be used, for example, in securesystems for providing a response enabling secure identification of thedevice. When the predetermined input is presented to the electronicdevices during use, different outputs are generated by eachindividualized electronic device, thus enabling secure identification ofthe device.

The features from which a selection is to be made for individualizing anelectronic device or a batch of electronic devices can be defined by afeature data set, which can be provided separately from design layoutdata which defines a common design layout applicable to all theelectronic devices. The feature data set and/or the common design layoutdata may be, for example, data files based on a GDSII or OASIS fileformat. In case a common design layout is used, a part of the commondesign layout (e.g. a part of the area of the layout) can be undefinedor left blank or set to a predetermined value, and the features for thispart of the design layout may be derived from the feature data set. Inthis way, the features selected from the feature data set can complementthe features defined in the design layout data, so that the commondesign layout and the selected features for individualizing theelectronic device together define the set of features for eachindividual electronic device.

It is also possible to create the individualized part of the electronicdevice and the common part of the electronic device separately. Forexample, the common design layout part may be created utilizingphotolithography at a relatively lower cost, while the individualizedpart may be created using a maskless lithography system. The to beindividualized part of the electronic device can be individualized byselecting different features for different subsets of the electronicdevices. The selection of the features can be made at a late processingstage close to or within the maskless lithographic exposure system,thereby minimizing the potential for public exposure of the specificfeatures used to individualize a particular electronic device.

According to an aspect of the invention a method of manufacturingelectronic devices is proposed, using a maskless lithographic exposuresystem. The maskless lithographic exposure system can use a masklesspattern writer. The method can comprise generating beamlet control datafor controlling the maskless pattern writer to expose a wafer forcreation of the electronic devices. The beamlet control data can begenerated based on a feature data set defining features selectable forindividualizing the electronic devices. Exposure of the wafer accordingto the beamlet control data can result in exposing a pattern having adifferent selection of the features from the feature data set fordifferent subsets of the electronic devices.

The maskless pattern writer may be a raster scanning based masklesspattern writer, in which case the beamlet control data may take the formof pattern bitmap data. The maskless pattern writer may be a vectorscanning based maskless pattern writer, in which case the beamletcontrol data may be formatted in a manner suitable for vector scanningOther types of maskless pattern writer may also be used.

The electronic devices can be individualized or made unique by adifferent selection of the features for each of the electronic devicesor subsets of the electronic devices. In this way, a set of electronicdevices may be manufactured which are partly identical and partlydifferent, i.e. having the same set of features formed in a common partof all of the electronic devices of the set, and having a set offeatures in an individualized part of the electronic device which isdifferent in each electronic device or in each subset of the electronicdevices. The set of electronic devices may, for example, consist of orinclude semiconductor chips all formed on a single wafer.

Advantageously the method enables the creation of the individualizedarea of the electronic devices to remain within the operations of themaskless lithographic exposure system and public exposure time of thedesign data of the individualized area is minimized.

In an embodiment, generating the beamlet control data can beadditionally based on design layout data defining structures applicablefor all of the electronic devices to be manufactured from the wafer. Thefeature data set can define the plurality of features selectable forcomplementing the structures defined in the design layout data. Thesestructures and features may be, for example, electronic circuit elementsor portions of circuit elements such as transistors, diodes, resistors,connecting lines, and/or vias, and the structures may be interconnectedto form an electronic circuit in the completed electronic device.

Advantageously the required processing power and memory for generatingthe beamlet control data may remain low, in that the design layout datacan be reused for the creation of multiple electronic devices, whereutilizing the known method of creating unique electronic devicesrequires design layout data for each unique electronic device and thuscapacity and processing time for each unique design manufactured.

In an embodiment the feature data set can comprise a plurality of datafiles, wherein each data file comprises a subset of the featuresapplicable to one of the different subsets of the electronic devices.Thus, the design layout of the part of the electronic device that is tobe individualized may be obtained from a file containing the featuresfor one individualized electronic device.

In an embodiment the feature data set can comprise a data file, whereinthe data file comprises a plurality of subsets of the features, whereineach subset of the features is applicable to one of the differentsubsets of the electronic devices. Thus, the design layout of the partof the electronic device that is to be individualized may be obtainedfrom a file containing the features for multiple individualizedelectronic devices.

In an embodiment the step of generating the beamlet control data can beadditionally based on selection data. The selection data can define aselection of the features of the feature data set for individualizingthe electronic devices, or in case the design layout data is used forcomplementing the structures for each electronic device to bemanufactured from the wafer. The selection data can define a differentselection of the features for different subsets of the electronicdevices. Thus, the design layout of the part of the chip that is to beindividualized can be generated based on the selection data, whichdefines the features that are selected for individualizing theelectronic devices, or in case the design layout data is used forcomplementing the structures for each subset of the electronic device tobe manufactured from the wafer.

In an embodiment at least one selection of the features of the featuredata set can comprise a plurality of at least one of the features. Thus,a feature defined in the feature data set may be selected and usedmultiple times.

In an embodiment the feature data set can define a plurality ofdifferent features. Thus, the feature data set may include featureswhich are different from one another, possibly only different features.

In an embodiment the feature data set can includes at least one of: acircular shaped feature; a feature shaped as a line having a firstorientation and having a first width; a feature shaped as a line havinga second orientation perpendicular to the first orientation; a featureshaped as a line having a second width different from the first width; afeature shaped as an elbow structure; a feature shaped as a rectangle; afeature shaped as a plus sign. A single feature may be shaped as acombination of two or more of such features. The features may enableelectrical connections within or between layers of the chip when exposedon the wafer.

In an embodiment the step of generating the beamlet control data can beadditionally based on feature meta data, wherein the feature meta dataspecifies a location where the features from the feature data set, whichcan be selected using the selection data, are to be created forindividualizing the electronic devices. This location can be thelocation of a to be individualized area in the chip design.

In an embodiment the features defined in the feature data set can beselected to be included in the beamlet control data on the basis of boththe feature meta data and the selection data.

In an embodiment the method can further comprise generating one or morebitmap fragments from the selected features, wherein each bitmapfragment defines a part of a stripe to be exposed on the wafer. Themethod can further comprise selecting a bitmap fragment from the one ormore bitmap fragments for inclusion in the beamlet control data based onthe feature meta data. Bitmap fragments may be used to complement acommon design bitmap or may be combined for the generation of a bitmapdefining a scan line or stripe to be exposed on the wafer.

The design layout data may be received in the maskless lithographicexposure system via a first network path. The selection data may bereceived in the maskless lithographic exposure system via a secondnetwork path separate from the first network path. This enablesprovisioning of the design layout data and the selection data from adifferent sources.

As the design layout data, for example in the form of a GDSII or OASISdata file, typically concerns large amounts of data while the selectiondata may take the form of a relatively small file, the first networkpath may have a higher data transmission bandwidth than the secondnetwork path. The first network path is for example based on fiberoptics network connections. The second network path is for example basedon cat6 Ethernet network connections.

Typically the selection data will be received from a source external tothe maskless lithographic exposure system, such as from a black boxdevice within a manufacturing part of the fab. In this example theselection data may advantageously be received via the second networkpath which may also be used to control the maskless lithographicexposure system. Thus, existing network interfaces may be used for theprovisioning of the selection data to the maskless lithographic exposuresystem.

The feature meta data typically concerns relatively small amounts ofdata and may be received in the maskless exposure system via the firstor the second network path.

In an embodiment the electronic devices can be semi-conductor chips andthe maskless pattern writer can be a charged particle multi-beamletlithography machine or e-beam machine.

The selection data may be received in an encrypted form to provideadditional data security within the fab in the process of creatingunique electronic devices.

The feature meta data may be encrypted to provide additional datasecurity within the fab in the process of creating unique electronicdevices.

The beamlet control data may be encrypted to provide additional datasecurity within the fab in the process of creating unique electronicdevices.

According to an aspect of the invention an electronic device such assemi-conductor chip is proposed, which is created using one or more ofthe above described methods.

In an embodiment the electronic device can be a truly uniquesemi-conductor chip different, e.g. functionally different, from anyother semi-conductor chip using the method of the invention.

According to an aspect of the invention a maskless lithographic exposuresystem is proposed configured to perform one or more of the abovedescribed methods.

In an embodiment the maskless lithography exposure system can comprise ablack box device that is configured to generate selection data defininga selection of the features of the feature data set for individualizingthe electronic devices to be manufactured from the wafer. The selectiondata can define a different selection of the features for differentsubsets of the electronic devices.

The black box may be owned by a third party, e.g. an IP block owner orthe owner of the manufactured chip, or a key management infrastructureowner. Advantageously the black box can be located within the fab closeto the operations of the lithography machine, thereby minimizing publicexposure of the selection data. This in contrast to known chipmanufacturing solutions, where a black box for individualizing chips istypically located outside of the fab and used to individualize the chipsafter being created.

According to an aspect of the invention a semiconductor fabricationplant is proposed comprising a maskless lithography exposure system asdescribed above.

According to an aspect of the invention a lithography subsystemcomprising a rasterizer and a maskless pattern writer is proposed. Themaskless pattern writer is e.g. a charged particle multi-beamletlithography machine or e-beam machine. The rasterizer can be configuredto generate beamlet control data for controlling the maskless patternwriter to expose a wafer for the creation of electronic devices. Thebeamlet control data can be generated based on a feature data setdefining features selectable for individualizing the electronic devices.Exposure of the wafer according to the beamlet control data can resultin exposing a pattern having a different selection of the features fromthe feature data set for different subsets of the electronic devices.

In an embodiment of the lithography subsystem, the generating of thebeamlet control data can be additionally based on selection data. Theselection data can define a selection of the features of the featuredata set for individualizing the electronic devices. The selection datacan define a different selection of the features for different subsetsof the electronic devices to be manufactured from the wafer. In anembodiment of the lithography subsystem, the generating of the beamletcontrol data can be additionally based on feature meta data.

Another aspect of the invention relates to an electronic device createdusing the method and/or the lithography subsystem described above.

Yet another aspect of the invention relates to an electronic devicecomprising a semiconductor chip which comprises a plurality ofstructures formed in three or more layers of the semiconductor chip,wherein the semiconductor chip is a member of a set of semiconductorchips, each of the semiconductor chips of the set having a set of commonstructures which are present in all of the semiconductor chips of theset and a set of non-common structures which are only present in asubset of the semiconductor chips of the set, and wherein the non-commonstructures are formed on at least a first one of the layers having asecond one of the layers above the first layer and having a third one ofthe layers below the first layer.

Yet a further aspect of the invention relates to an electronic devicecomprising a semiconductor chip which comprises a plurality ofstructures formed in a plurality of layers of the semiconductor chip,wherein the semiconductor chip is a member of a set of semiconductorchips, each of the semiconductor chips of the set having a set of commonstructures which are present in all of the semiconductor chips of theset and a set of non-common structures which are only present in asubset of the semiconductor chips of the set, and wherein the non-commonstructures include at least one of: connections between metal layers ofthe plurality of layers; connections between a metal layer and a gate ina contact layer of the plurality of layers; connections in a localinterconnect layer of the plurality of layers; and a P- or N-dopeddiffusion region of a transistor or diode of one of the plurality oflayers.

In the electronic devices described above, the common structures and thenon-common structures of the semiconductor chip may be interconnected toform an electronic circuit. The electronic device may comprise at leastone input terminal for receiving a challenge and at least one outputterminal for outputting a response. The electronic circuit may form achallenge-response circuit connected to the at least one input terminaland the at least one output terminal, and the challenge-response circuitmay be adapted for generating a response at the at least one outputterminal based on a challenge applied to the at least one inputterminal, the challenge and the response having a predeterminedrelationship.

Various aspects and embodiments of the invention are further defined inthe following description and claims.

Hereinafter, embodiments of the invention will be described in furtherdetail. It should be appreciated, however, that these embodiments maynot be construed as limiting the scope of protection for the presentinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will now be described, by way of example only, withreference to the accompanying schematic drawings in which correspondingreference symbols indicate corresponding parts, and in which:

FIG. 1a shows a simplified unique chip of an exemplary embodiment of theinvention;

FIG. 1b shows a wafer with multiple unique chips of an exemplaryembodiment of the invention;

FIG. 2 shows a schematic diagram of systems involved in themanufacturing of electronic devices according to an exemplary embodimentof the invention;

FIG. 3 shows a functional flow diagram of the creation of pattern bitmapdata of an exemplary embodiment of the invention;

FIG. 4 represents a field defined by design layout data and a featuredata set in the form of separate data files according to an exemplaryembodiment of the invention;

FIG. 5 represents a field defined by design layout data and a featuredata set in the form of a single data file according to an exemplaryembodiment of the invention;

FIG. 6a represents a field defined by design layout data, feature metadata and a feature data set in the form of a set of individual featuresaccording to an exemplary embodiment of the invention;

FIG. 6b represents selection data according to an exemplary embodimentof the invention;

FIG. 7 shows a functional flow diagram of the creation of pattern bitmapdata, according to an exemplary embodiment of the invention;

FIG. 8 shows a functional flow diagram of the creation of pattern bitmapdata, according to another exemplary embodiment of the invention;

FIG. 9 shows a simplified schematic drawing of an exemplary embodimentof a charged particle multi-beamlet lithography system; and

FIG. 10 is a conceptual diagram showing an exemplary masklesslithography system.

The figures are meant for illustrative purposes only, and do not serveas restriction of the scope or the protection as laid down by theclaims.

DESCRIPTION OF EMBODIMENTS

In the following examples reference is made to semi-conductor chips, butit is to be understood that the invention is not limited to chips andapplies more generally to the creation of electronic devices havingindividualized, e.g. unique features. The electronic device may be aread only memory (ROM). For example, batches of chips withindividualized ROM load may be created using the invention. Such batchesare typically small batches, e.g. created from one or less than onewafer.

The process performed by charged particle multi-beamlet lithography isalso being referred to as an electron beam or e-beam exposure. Theelectron beam exposure method is a maskless exposure method. Theelectron beams used for writing a target such as a wafer during electronbeam exposure are also being referred to as beamlets.

Unique chips are designed to be unique with respect to other chips. Thisdoes not exclude the possibility that more than one unique chip can bemade using the invention, for example to create a spare unique chip foruse in case the original unique chip is damaged, to created batches ofthe same chip or for any other reason. A unique semi-conductor chip thatis functionally different from any other semi-conductor chip may bereferred to as a truly unique chip. The creation of a visually readableunique ID on a chip may also be regarded as creating a unique chip.Copies of the unique chip may be made by repeating the creation of thechip on different wafers or a single wafer may include one or morecopies of the unique chip.

FIG. 1a shows an exemplary simplified unique chip 100 containing acommon part 101 and an individualized area 102. FIG. 1b shows anexemplary wafer 24 with unique chips created thereon. The common part101 may be replicated in other chips created on the wafer 24 resultingin multiple chips having the same identical part. The individualizedarea 102 may be different from other chips created on the wafer 24. Thisis illustrated in FIG. 1b where the wafer 24 is shown containing aunique chip 100 and 39 other unique chips, each unique chip having adifferent individualized area. The combined common part 101 andindividualized area 102 may result in unique chip 100.

The individualized area 102 may be realized by selecting and writingspecific features, which are selectable from a feature data set. Otherunique chips may have a different selection of the features from thefeature data set, resulting in the realization of differentinterconnections within a layer or between layers of the electroniccircuit.

The common part 101 may be created using photolithography, but ispreferably created using charged particle multi-beam lithography. Theindividualized area is typically created using charged particlemulti-beam lithography.

FIG. 2 shows a semiconductor fabrication plant 1000, including systemsand processes involved in the manufacturing of unique semi-conductorchips, of an exemplary embodiment of the invention. In case referencenumbers used in FIG. 2 refer to processes or operations, these referencenumbers may also refer to computational units performing the processesor operations. Each of the shown processes and operations may beperformed by a dedicated unit. Alternatively, one computational unit mayperform multiple processes or operations shown in FIG. 2. Acomputational unit is for example a computer system including one ormore processors and memory for running dedicated tasks or for runningprograms under an operating system.

The semiconductor fabrication plant 1000 may include a production setuppart 1002 and a manufacturing part 1003. It is possible that no divisionis made into the two parts 1002 and 1003 or that another division ismade. The manufacturing part 1003 may include one or more lithographysubsystems 1070 each using a maskless pattern writer 1073. In thisexample the maskless lithographic exposure system is a charged particlemulti-beamlet lithography system and the maskless pattern writer 1073 isa charged particle multi-beamlet lithography machine or e-beam machine.

At the left hand side of FIG. 2 a standard IC design flow 1001 is shownthat typically results in the creation of mask order data, design layoutdata and/or wafer order data, jointly depicted as output 2000. Thedesign layout data is typically generated in a GDSII or OASIS dataformat. The standard IC design flow is known in the art and typicallyincludes a system/full IC design stage 1010, a circuit designVHL/Verilog stage 1011, a logical verification stage 1012, a placement &routing (P&R) stage 1013, a physical simulation stage 1014 and/or adesign rule checks (DRC) stage 1015.

A process design kit 1030 including an add-ons and IP library mayprovide the building blocks in the form of reusable units of logic, cellor chip layout designs from a function IP blocks storage 1031 to varioussteps in the standard IC design flow 1001, as depicted by the arrowsfrom the function IP blocks storage 1031 to steps 1011, 1012, 1013, 1014and 1015 of the standard IC design flow 1001. The process design kit1030 is typically located within the production setup part 1002 of thefab 1000, as it may concern function IP blocks licensed from an IP blockdesigner 1005 to the chip manufacturer.

The created design layout data typically includes a common design layoutpart defining layout structures applicable for all of the chips to becreated. Furthermore the design layout data may include a non-commondesign layout part, which may be left blank or undefined. The non-commondesign layout part will be filled in at a later stage with featuresselected from a feature data set for individualizing the chips.

The feature data set may be provided together with or separate from thedesign layout data. Alternatively, the feature data set may bepredefined, stored and retrievable within the fab for each use.

The output 2000 of the design flow 1001 may be provided to the chargedparticle multi-beamlet lithography system via a tape-out and sign-offprocess 1016. More specifically, the output 2000 may be input to apreparation part 1020 of the production setup 1002 where an opticalproximity correction (OPC) operation 1021, a data preparation (PEC,fracturing) operation 1022, a recipe/process program (PP) generationoperation 1023 and/or an order and production planning operation 1024may be performed. The output of each of these operations may betransferred to the manufacturing part 1003 passing a verification step1040.

In case a photolithography exposure is to be performed to a wafer priorto the maskless lithographic exposure, optical proximity correction(OPC) 1021 may be applied to the GDSII design layout data, resulting incorrected GDSII data 2010, which may be input to a mask shop 1081together with the mask order data. This may result in a mask set 2011that may be input to a reticle stocker 1082 from where reticles (masks)2012 may be input to the CMOS wafer flow 1080. The wafer order data maybe used to have wafers 1083 input to the CMOS wafer flow 1080 whenneeded. The photolithography exposure itself is not shown in FIG. 2. Theresulting exposed wafer is shown as wafer 2013. Note that in case nophotolithographic exposure is performed, the wafer 2013 may be anunexposed wafer.

The data preparation unit 1022 may pre-process the GDSII design layoutdata depicted as 2007 into pre-processed design layout data 2008. Thepre-processed design layout data 2008 may include data specific to thelithography subsystem 1070. This off-line preprocessing of the GDSIIdata 2007 may include steps like flattening, proximity correction,resist heating correction and/or drawing of smart boundaries. Thepattern vector data 2008 may be stored in a reticle storage 1051 ofmanufacturing execution system (MES) 1050.

The recipe/PP generation 1023 may generate instructions for the creationof process jobs (PJs). The PP and associated programs may be stored in arecipe/PP database 1052 of the MES 1050. A PP 2005 may be sent from theMES 1050 to a machine control 1072 of the lithography subsystem 1070 toinstruct the machine control 1072 to create a PJ based on the PP.Additional commands may include Abort and Cancel instructions.

For example, via the order and production planning 1024 themanufacturing database 1053 of the MES 1050 may be provided withmanufacturing specific information. From here a PJ input generator 1054may be fed with information. The PJ input generator 1054 may provide PJinput to machine control 1072, where PJs 2006 may be generated forcontrolling parts of the lithography subsystem 1070, in particularrasterizer 1071 and pattern streamer (maskless pattern writer) 1073.

The operation of the lithography subsystem 1070 may be controlled usingthe PP, which may comprise a sequence of actions to be performed. Themachine control 1072 may be loaded with a PP, and may schedule andexecute the PP as may be requested by the recipe/PP generation 1023. ThePP may take the role of a recipe, e.g. as defined in the SEMI E40standard. Although the SEMI standards specify many requirements on howto deal with recipes, the standards may be contradictory so that recipesare preferably avoided. Instead, editable and unformatted PP may be usedin the form of so-called Binary Large Objects (BLOBs).

The PP may be a pre-planned and reusable portion of the set ofinstructions, settings and/or parameters that may determine theprocessing environment of the wafer and that may be subject to changebetween runs or processing cycles. PPs may be designed by lithographytool designers or may be generated by tooling.

PPs may be uploaded to the lithography system by a user. PPs may be usedto create PJs. A PJ may specify the processing to be applied to a waferor set of wafers by the lithography subsystem 1070. A PJ may definewhich PP to use when processing a specified set of wafers and mayinclude parameters from the PP (and optionally from the user). A PJ maybe a system activity started by a user or host system.

PPs may be used not only for controlling the processing of wafers, butalso for service actions, calibration functions, lithography elementtesting, modifying element settings, updating and/or upgrading software.Preferably no subsystem behavior occurs other than what is prescribed ina PP, with the exception of certain allowed additional categories, suchas automatic initialization during power-up of a module or subsystem,periodic and unconditional behavior of a subsystem, as far as thosedon't influence PJ execution, and the response to an unexpectedpower-off, emergency or EMO activation.

A PP may be divided into steps. Most steps typically comprise a commandand identify a subsystem which is to perform the command. The step mayalso include parameters to be used in performing the command, andparameter constraints. The PP may also include scheduling parameters toindicate when a step is to be performed, e.g. to be performed inparallel, in sequence, or synchronized.

To execute a command step of the PJ, the machine control 1072 may sendthe command indicated in the PJ to the subsystem indicated in therelevant step of the PJ. The machine control 1072 may monitor timing andmay receive the results from the subsystem.

The pre-processed design layout data 2008 is typically stored in thereticle storage 1051 in a tool input data format, which is a vectorformat and includes dose information. The pre-processed design layoutdata 2008 may be provided from the reticle storage 1051 to therasterizer 1071 of the lithography subsystem 1070, where it may beprocessed into beamlet control data such as pattern bitmap data 2009 forcontrolling the maskless pattern writer 1073 to expose a wafer forcreation of the chip.

A feature data set 2016 defining features selectable for individualizingthe chips may be provided in various manners. In one example the featuredata set 2016 may be provided to the rasterizer 1071 using the samenetwork path as used for providing the pre-processed design layout data2008, as shown in FIG. 2. In another example the feature data set 2016may be provided with the PP 2005 to the lithography subsystem 1070. Inanother example the feature data set 2016 may be provided to thelithography subsystem 1070 via PJ input generator 1054. In anotherexample the feature data set 2016 may be provided to a black box device1060. The feature data set 2016 may be stored within the fab or providedfrom an external source before use.

The pre-processed design layout data 2008 may include the structuresapplicable for all of the chips to be manufactured from the wafer. Theselection of the features from the feature data set for individualizingthe chips may be made based on input from a secured, in-fab black boxdevice 1060, which may generate selection data defining a selection ofthe features of the feature data set such that a different selection ofthe features may be made for different chips to be manufactured from thewafer. Alternatively, the black box device 1060 provides subsets of thefeatures applicable to each of the chips to be manufactured, whereineach subset of the features is different. Such subset of features may beprovided as a GDSII or OASIS file, which will be relatively small as itonly includes the design layout of the non-common, i.e. individualizedpart of the chip.

The feature data set may include a plurality of different features, suchas a circular shaped feature, a feature shaped as a horizontal line, afeature shaped as a vertical line or a cross shaped feature. From thisfeature data set features may be selected and used multiple times todefine the individualized part of the chip. Selection data may be usedto indicate which of the features from the feature data set are to beused.

The selection data, which is depicted as 2004 in FIG. 2, may be providedfrom the black box device 1060 to the PJ input generator 1054.Preferably, the selection data 2004 is encrypted. The PJ input generator1054 may send the selection data 2004 to the machine control 1072, wherea PJ 2006 may be generated instructing the rasterizer 1071 to obtain theindicated features from feature data set and generate the pattern bitmapdata 2009 based on the selected features.

Alternatively, the black box device 1060 may be configured to providethe selection data 2004 directly to the lithography subsystem 1070 forprovisioning the selection data 2004 to the rasterizer 1071 withoutinvolving the PJ input generator 1054.

The feature data set may be provided as a single file, such as a GDSIIor OASIS based file. To locate where the selected features from thefeature data set are to be created in the to be individualized chipdesign, feature meta data may be provided. The feature meta data,depicted 2003 in FIG. 2, may be received together with the feature dataset in the preparation part 1020. From there the feature meta data 2003may be provided to the black box device 1060, e.g. via the recipe/PPgenerator 1023 or via the order and production planning 1024. The latterscenario is shown in FIG. 2, where the feature meta data 2003 followsthe route from the order and production planning 1024 to the black boxdevice 1060 via the manufacturing database 2003. The black box 1060 mayprovide the feature meta data 2003 to the lithography subsystem 1070following the same route as the selection data described above, e.g. viathe PJ input generator 1054, or directly to the lithography subsystem1070. Alternatively, the feature meta data may be provided to thelithographic subsystem using any of the available network paths.

The black box device 1060 may include an ID/key manager 1061 and aselection data generator 1062 that cooperate in the creation of theselection data 2004. The ID/key manager 1061 may receive productID/serial number information 2001 from the manufacturing database 1053and batches of ID/key pairs 2002 from a key management service 1006possibly located outside of the maskless lithographic exposure system.The product ID/serial number information 2001 and the batches of ID/keypairs 2002 may be used to control the generation of the selection data2004. Furthermore, the product ID/serial number information 2001 may beused to track the chips through the creation process to be able thechips to be matched with their ID/serial numbers after being created.Alternatively or additionally, the product ID/serial number information2001 may be used to include the ID/serial number in or on the chip by anot shown but known per se process.

Exposure of the wafer 2013 according to the pattern bitmap data 2009 mayresult in exposing a pattern having a different selection of thefeatures from the feature data set for different subsets of the chips.In FIG. 2 this is depicted as exposed wafer 2014. The exposed wafer 2014may further be processed in accordance with the standard CMOS wafer flow1080 typically including inspection, etching, deposition CMP and/orslicing steps. The resulting sliced chips 1007 may be unique chips thatmay be used e.g. in an end-user device 1008 for data security,traceability and/or anti-counterfeiting applications. Arrow 2015 depictsthe provisioning of a unique chip to the end-user device 1008.

Process programs (PP) and process jobs (PJ) may be based on the SEMIstandard, e.g. SEMI E30: “Generic Model for Communications and Controlof Manufacturing Equipment (GEM)”, SEMI E40: “Standard for ProcessingManagement”, SEMI E42: “Recipe Management Standard: Concepts, Behavior,and Message Services”, and/or SEMI E139: “Specification for Recipe andParameter Management (RaP)”.

FIG. 3 shows an exemplary functional flow diagram of a data path usingreal-line rasterization, which may be followed in the generation of thepattern bitmap data 2009 from the GDSII design layout data 2007. Thefunctional flow of FIG. 3 may be used in the maskless lithographicexposure system of FIG. 2. In FIG. 3 the functional flow diagram issplit into four sections: 3010 is used to indicate a data format ofunderlying data outputs/inputs; 3020 shows the process flow includingdata outputs/inputs (parallelograms) and functional elements(rectangles); 3030 is used to indicate process steps performed atoverlying functional elements; and 3040 is used to indicate how oftenthe process steps are typically performed, e.g. once per design 3041,once per wafer 3042 or once per field 3043. Roman I, II and III indicatewhen the feature data set and/or the selection data may be provided tothe data path.

Input to the process may be the GDSII design layout data 2007, or adesign layout in any other suitable format such as an OASIS data format.The GDSII design layout data 2007 may include blank parts or undefinedparts where the individualized part is to be inserted.

Data preparation unit 1022 may pre-processes the GDSII file 2007,typically as an off-line pre-processing operation. The pre-processingoperation typically includes one or more of a flattening, a proximitycorrection, a resist heating correction and/or drawing of smartboundaries operation, jointly depicted as 3031. Output of the datapreparation 1022 may be the pre-processed design layout data 2008typically in a vector format including dose information, depicted as3011. The format of the pre-processed design layout data 2008 is alsoknown as a tool input data format. The data preparation 1022 istypically performed once per design depicted by arrow 3041, but may beperformed once per wafer or once per field.

The pre-processing at the data preparation unit 1022 preferably does notexpose a specific or unique chip design, i.e. the selection data 2004 ispreferably not available at this stage in the data path, advantageouslyallowing the data preparation unit 1022 and the production setup part1002 of the fab to be located in a less secure environment.

As described above, it is desirable to minimize exposure and exposuretime of the specific or unique chip design part for security reasons.The security aspect is important as the uniqueness of the chip willtypically be used for data security, traceability and/oranti-counterfeiting applications. The processes within the dashed block,i.e. from software processing 1071A until hardware processing at thepattern writer 1073, are typically performed within the lithographysubsystem 1070 enabling a more secure operating environment.Furthermore, by providing the selection data 2004 only at the softwareprocessing 1071A or later, the amount of time that the unique featuresof the chips is used within the manufacturing part 1003 of the fab maybe minimized.

The selection data 2004 is typically provided and used once per field.Roman III indicates the provisioning of the selection data 2004 to thedata path at this stage. Alternatively but less preferred, the selectiondata 2004 may be provided and used once per wafer. Roman II indicatesthe provisioning of the selection data 2004 to the data path at thisstage.

The feature meta data 2003 may be provided to the lithography subsystem1070 together with the selection data 2004, as described with FIG. 2.Alternatively, the feature meta data may be provided once per design, asindicated with roman I.

The pre-processed GDSII design layout data 2008 may be input to arasterizer 1071, which may includes a software processing part 1071A anda streaming part 1071B as shown in FIG. 3. Depending on whether theselection data 2004 is to be used once per wafer as depicted by roman IIor once per field as depicted by roman III, the software processing part1071A or the streaming part 1071B may use the selection data 2004together with the feature meta data 2003 to select the features from thefeature data set as defined by the selection data 2004.

In-line processing of the pre-processed design layout data 2008 may beperformed at the software processing part 1071A to rasterize the vectordata to generate pattern system streaming (PSS) data 3021. The PSS data3021 may be formatted as 4 bit greyscale bitmap data depicted as 3012.

The rasterizing may be performed in software. The unique chip designpart may be realized at this stage, as indicated by roman II. Thestreaming part 1071B may then processes the PSS data 3021 to generatethe pattern bitmap data 2009. Processes performed by the streaming part1071B may include corrections involving a full or partial pixel shift inthe X and/or Y direction for beam position calibration, field sizeadjustment and/or field position adjustment on the bitmap data. Theseprocesses are jointly depicted as 3032. Alternatively to entry point II,the unique design part may be realized at this stage, as indicated byroman III. The pattern bitmap data 2009 may be streamed to a patternwriter 1073 for exposure of the wafer. This streaming of the patternbitmap data 2009 is depicted as 3022.

Rasterization may be performed at the streaming stage 1071B, which mayinvolves real-time processing performed in hardware. Corrections forbeam position calibration, field size adjustment, and/or field positionadjustment (jointly depicted 3032) may be made on the vector format PSSformat data 3021, and then rasterization may convert this to a patternbitmap data. When the corrections are made on vector data, full pixelshifts, partial pixel shifts and/or subpixel shifts in the X and Ydirection may be made.

The controlling of the maskless pattern writer 1073 typically involves ablanker being controlled by the pattern bitmap data. The pattern bitmapdata 2009 may also be referred to as blanker format data.

FIG. 4 shows an exemplary embodiment of a field 103 defined by designlayout data and a feature data set in the form of separate data files2016 a. In this example the design layout data defines four unique chipswithin the field, each chip having a common part 101 that may beidentical in all four chips and a to be individualized area 102 that isblank or undefined in the design layout data. The roman I, II and IIIindicate when, in this example, the respective data may be provided tothe data path of FIG. 3.

Each data file 2016 a may include a subset of features applicable to oneof the chips and may be in a GDSII or OASIS based data format. Theblack-box device 1060 may be used to create and/or assign the data files2016 a to the different chips, thereby making the selection of thefeatures to be used to individualize the chips.

The rasterizer 1071 may receive the selected files or an indication ofwhich of the data files 2016 a to use relevant to the fields that aregoing to be exposed on the wafer.

In the example of FIG. 4 the number of data files 2016 a may be verylarge, which could have a negative impact on data processing time asfile I/O operations will be more frequent. In the example of FIG. 5 thisproblem has been overcome by storing a plurality of subsets of featuresinto a single data file 2016 b. As in FIG. 4, each block of the featuredata set, in FIG. 5 included in the single data file 2016 b, mayrepresent a design layout for the individualized area 102 of a chip andmay be stored in a GDSII or OASIS based data format. Use of the featuredata set in the example of FIG. 5 is similar to FIG. 4.

In the examples of FIG. 4 and FIG. 5 all possible design layouts of theindividualized areas 102 for the chips to be manufactures are typicallyprepared and stored before use, while the selection of the subset of thefeatures to be used for a particular chip may be made at a late stage,e.g. within the black box device 1060. In the example of FIG. 6a andFIG. 6b the design layout of the individualized areas need not bepre-stored and may also be created at a late stage, e.g. within theblack box device 1060 or even at a later stage such as within therasterizer 1071.

FIG. 6a shows an exemplary embodiment of a field 103 defined by designlayout data, feature meta data 2003 and a feature data set 2016 c. Inthis example the design layout data defines four unique chips within thefield, each chip having a common part 101 that may be identical in allfour chips and a to be individualized area 102 that is blank orundefined in the design layout data. The roman I, II and III indicatewhen, in this example, the respective data may be provided to the datapath of FIG. 3.

In this example the feature data set 2016 c includes features A-E.Feature A represents a circular shaped feature, feature B represents afeature shaped as a horizontal line, feature C represents a featureshaped as a vertical line, feature D represents a cross shaped feature,and feature E represents a transparent/blank feature. The feature dataset 2016 c may include any number of features and may include other ordifferent shapes than shown in FIG. 6a . Non limiting examples of otherfeatures not shown in FIG. 6a are lines of different width, circles,lines with different orientations, elbow structures with differentorientations, rectangles, and combinations of shapes in a singlefeature.

Preferably, the feature data set 2016 c includes a plurality ofdifferent features. The feature data set 2016 c typically does notinclude indicators A-E, which are shown in FIG. 6a for illustrativepurposes only. The features may be stored in the feature data set 2016 cin any suitable data format, e.g. using a GDSII or OASIS based dataformat.

Feature meta data 2003 may be used to indicate a location of anindividualized area 102 where selected features from the feature dataset 2016 c are to be created. Feature1 as indicated in the feature metadata 2003, may corresponds to the top left individualized area, which isdepicted by the reference number 102. According to the feature meta data2003 the location within the chip design of Feature1 is X0,Y0.Similarly, Features2 to FeatureN may define the locations of otherindividualized areas where selected features from the feature data set2016 c are to be created. In this example the coordinates of eachfeature are represented as an X,Y location. It will be understood thatany other coordination system or indication of a location within thedesign layout may be used instead.

The feature meta data 2003 may include, in addition to the locationinformation, additional information, such as a width and/or a height ofthe individualized areas 102. The feature meta data may be optimized,e.g. by including meta data common to multiple features only once.

FIG. 6b shows an exemplary embodiment of selection data 2004, which maybe used together with the example of FIG. 6a . The selection data 2004may contain a list of fields and for each field n letters indicatingwhich feature is to be included. Letter A-E as shown in FIG. 6b may beused as an indication of a feature, or any other indication such as a4-bit nibble or 8-bit byte. In the example of FIG. 6b n equals 10, i.e.ten features are selected per field. The location of the selectedfeature within the field may correspond with the index of thecorresponding letter, i.e. the order of the letters as defined for eachfield in the selection data 2004 may define the order of thecorresponding features in the field. In this example the fields arenumbered from Field1 to FieldM, M being any positive index number. Itwill be understood that any other identification of the fields may beused instead or the identification of the fields may be left outcompletely using the position of each set of field letters within a file(e.g. counting the line numbers) as identification of the fields.

The rasterizer 1071 may receive the selection data 2004 or a subset ofthe selection data relevant to the fields that are going to be exposedon the wafer. The selection data 2004 may be used to create the selectedfeatures from the feature data set 2016 e at the locations as defined bythe feature meta data 2003.

FIG. 7 represents a data flow in a part of a data path involved in thecreation of pattern bitmap data 2009, according to an exemplaryembodiment of the invention. Data is indicated as parallelograms andprocess steps are indicated as rectangular boxes.

At the start of the data flow on the left, pre-processed design layoutdata 2008 may have been processed into an intermediate 4 bits-per-pixelgrey level bitmap 3021B, or any other suitable bitmap format, by arasterizer 1071 e.g. as shown in FIG. 2 or any other processing unit,preferably part of a lithography subsystem 1070. This intermediate 4 bppgrey level bitmap 3021B may include the structures of the common part101 of the chips to be created. The to be individualized part of thechip design may be left blank in the intermediate 4 bpp grey levelbitmap 3021B. Optionally the intermediate 4 bpp grey level bitmap is ina compressed format 3021A and decompressed in a decompression step 3035.ZIP compression or any other suitable compression format may be used asa compression format.

On the top right, feature meta data 2003, selection data 2004 and afeature data set 2016 c may be used to create a 4 bits-per-pixel greylevel bitmap mask 3023A, or a mask in any other suitable bitmap format,using a mask creation process 3033. The mask data 3023A is typically ina form allowing it to function as an overlay mask for complementing theintermediate bitmap 3021B by filling the blanks of the intermediatebitmap 3021B with individualized areas 102 defined by the mask 3023A.The mask data 3023A may be formatted in a sparse bitmap format, allowingthe mask data 3023A to be compressed with a high compression rate. Themask data 3023A may be intermediately stored in a compressed format anddecompressed, possibly in real-time, before use in merger operation3034.

In a merger operation 3034 the intermediate 4 bpp grey level bitmap3021B and the mask data 3023A may be merged, e.g. using an OR operation,resulting in the blank areas that are to be individualized in theintermediate bitmap 3021B to be filled in with the bitmap informationfrom the mask data 3023A. Possibly, only a part of the intermediate 4bpp grey level bitmap 3021B and a part of the mask data 3023A needed forthe part of the wafer to be exposed just ahead in time are used in themerger operation 3034.

The resulting 4 bpp grey scale bitmap 3021C may be processed for patternstreamer corrections and a B/W dithering operation may be performed, asindicated as processing step 3032A. Processing step 3032A may be similarto operation 3032 of FIG. 3. This may results in the pattern bitmap data2009 for controlling a maskless pattern writer, such as the masklesspattern writer 1073 of FIG. 3.

The processes 3033, 3034, 3035 and 3032A may be performed by arasterizer 1071 or any other processing unit, preferably part of alithography subsystem 1070. Processes 3032A, 3034 and/or 3035 may beperformed in real-time. Typically, one or more of the process stepsshown in FIG. 7 are performed in RAM memory and the mask data 3023A (ora part thereof), the intermediate 4 bpp grey level bitmap 3021B and/orthe 4 bpp grey scale bitmap 3021C are stored in RAM memory only duringprocessing of the data into the pattern bitmap data 2009. For increasedprocessing performance, preferably the merger operation 3034 andpossibly also the decompression operation 3035 are implemented inhardware, e.g. in FPGA or ASIC.

In an exemplary embodiment the intermediate 4 bpp grey scale bitmap3021B may define a stripe of a field of a wafer, e.g. covering an areaof 2 μm by 33 mm of the wafer. Each 4 bits pixel of the intermedia 4 bppgrey scale bitmap 3021B may cover an area of 5.4 nm by 5.4 nm. The mask3023A may be a 4 bpp bitmap covering one stripe or scan line on thewafer, e.g. covering an area of 2 μm by 300 mm Each 4 bits pixel of themask 3023A may cover an area of 5.4 nm by 5.4 nm in this example. Thus,the mask may have the same resolution as the intermediate 4 bpp greyscale bitmap, resulting in the merger operation 3034 to complement theblanks in the intermediate bitmap 3021E with the data from the mask3023A.

Optionally the mask data 3023A, especially when in a sparse bitmapformat, may be stored in a compressed format in RAM and decompressed onthe fly when performing the merger operation 3034.

FIG. 8 represents a data flow in a part of a data path involved in thecreation of pattern bitmap data 2009, according to another exemplaryembodiment of the invention. Data is indicated as parallelograms andprocess steps are indicated as rectangular boxes.

At the start of the data flow on the left, pre-processed design layoutdata 2008 may have been processed into an intermediate 4 bits-per-pixelgrey level bitmap 3021B, or any other suitable bitmap format, by arasterizer 1071 e.g. as shown in FIG. 2 or any other processing unit,preferably part of a lithography subsystem 1070. This intermediate 4 bppgrey level bitmap 3021B may include the structures of the common part101 of the chips to be created. The to be individualized part of thechip design may be left blank in the intermediate 4 bpp grey levelbitmap 3021B. Optionally the intermediate 4 bpp grey level bitmap is ina compressed format 3021A and decompressed in a decompression step 3035.ZIP compression or any other suitable compression format may be used asa compression format.

Feature meta data 2003, selection data 2004 and/or a feature data set2016 c may be used to create a number of 4 bits-per-pixel grey levelbitmap fragments 3023C-3023F, or fragments in any other suitable bitmapformat, using a fragment creation process 3036. One fragment 3023C-3023Fmay include bitmap information for one unique chip or one batch ofunique chips. Typically the number of fragments 3023C-3023F correspondswith the number of unique parts that will be written on the wafer witheach scan line or stripe. The fragments 3023C-3023F may be updated justbefore each scan line (or stripe) exposure of the wafer. Alternatively,fragments 3023C-3023F may be created and temporarily stored before beingused.

The feature meta data 2003, selection data 2004 and/or a feature dataset 2016 e may further be used to create a fragment assignment table3023B using a table creation process 3037. The table 3023B may indicatewhere fragments, e.g. the fragments 3023C-3023F, are to be written onthe wafer. The table 3023B may include information for all fragmentsthat are to be written on the wafer with one scan line or stripe, inwhich case the table 3023B may be updated before each scan.Alternatively, the table 3023B may include information for less or formore fragments, in which case the frequency of updating the table 3023Bwill be adapted accordingly. The fragment assignment table 3023B may bein any suitable data format, e.g. in the form of a data table or anyother data format.

The fragments 3023C-3023F are typically in a form allowing it to beinserted into the intermediate bitmap 3021B by filling blanks of theintermediate bitmap 3021B with (parts of) the individualized areas 102defined by the fragments 3023C-3023F.

In an insertion operation 3038 the fragments 3023A-3023F may be insertedinto the intermediate 4 bpp grey level bitmap 3021B under control of thefragment assignment table 3023B. An OR operation or any other suitableoperation may be used for the insertion operation 3038. The insertionoperation results in the blank areas that are to be individualized inthe intermediate bitmap 3021B to be filled in with the bitmapinformation from the assigned fragments 3023C-3023F. Possibly, only apart of the fragments 3023C-3023F, a part of the intermediate 4 bpp greylevel bitmap 3021B and a part of the fragment assignment table 3023Bneeded for the part of the wafer to be exposed just ahead in time areused in the insertion operation 3038.

The resulting 4 bpp grey scale bitmap 3021C may be processed for patternstreamer corrections and a B/W dithering operation may be performed, asindicated as processing step 3032A. Processing step 3032A may be similarto operation 3032 of FIG. 3. This may results in the pattern bitmap data2009 for controlling a maskless pattern writer, such as the masklesspattern writer 1073 of FIG. 3.

The processes 3035, 3036, 3037, 3038 and 3032A may be performed by arasterizer 1071 or any other processing unit, preferably part of alithography subsystem 1070. Processes 3035 and/or 3038 may be performedin real-time. Preferably, one or more of the process steps shown in FIG.7 are performed in RAM memory and the fragment assignment table 3023B,the fragments 3023C-3023F, the intermediate 4 bpp grey level bitmap3021B and/or the 4 bpp grey scale bitmap 3021C, or parts thereof, arestored in RAM memory only during processing of the data into the patternbitmap data 2009. For increased processing performance, preferably theinsertion operation 3038 and possibly also the decompression operation3035 are implemented in hardware, e.g. in FPGA or ASIC.

In an exemplary embodiment the intermediate 4 bpp grey scale bitmap3021B may define a stripe of a field of a wafer, e.g. covering an areaof 2 μm by 33 mm of the wafer. Each 4 bits pixel of the intermedia 4 bppgrey scale bitmap 3021B may cover an area of 5.4 nm by 5.4 nm. Thefragments 3023C-3023F may be 4 bpp bitmaps covering a part of one stripeor scan line on the wafer. Thus, the fragments may have the sameresolution as the intermediate 4 bpp grey scale bitmap, resulting in theinsertion operation 3038 to complement the blanks in the intermediatebitmap 3021B with the data from the fragments 3023C-3023F. The fragmentassignment table 3023B may include the information needed to select thefragment to be inserted for the current scan line or stripe. Hereto thetable 3023B may include scan line numbers assigned to fragments.

In the example of FIG. 8, fragments 3023C-3023F may be used tocomplement an intermediate 4 bpp grey level bitmap 3021B that mayinclude the structures of the common part 101 of the chips to becreated. In an alternative embodiment the 4 bpp grey scale bitmap 3021Cmay be created from fragments 3023C-3023F only, i.e. without anintermediate 4 bpp grey level bitmap 3021B, and under control of afragment assignment table 3023B. In this example the selected fragmentsmay be inserted into the 4 bpp grey scale bitmap 3021C by insertionoperation 3038, and together may include all the structures to becreated with the next scan line or stripe exposure of the wafer.

FIG. 9 shows a simplified schematic drawing of an exemplary embodimentof a charged particle multi-beamlet lithography machine 1, which may beused for implementing the maskless pattern writer 1073. Such alithography machine suitably comprises a beamlet generator generating aplurality of beamlets, a beamlet modulator patterning said beamlets intomodulated beamlets, and a beamlet projector for projecting said beamletsonto a surface of a target. The target is for example a wafer. Thebeamlet generator typically comprises a source and at least one aperturearray. The beamlet modulator is typically a beamlet blanker with ablanking deflector array and a beam stop array. The beamlet projectortypically comprises a scanning deflector and a projection lens system.

The lithography machine 1 may comprise an electron source 3 forproducing a homogeneous, expanding electron beam 4. Beam energy ispreferably maintained relatively low in the range of about 1 to 10 keV.To achieve this, the acceleration voltage is preferably low, theelectron source preferably kept at between about −1 to −10 kV withrespect to the target at ground potential, although other settings mayalso be used.

The electron beam 4 from the electron source 3 may pass a doubleoctopole and subsequently a collimator lens 5 for collimating theelectron beam 4. As will be understood, the collimator lens 5 may be anytype of collimating optical system. Subsequently, the electron beam 4may impinge on a beam splitter, which is in one suitable embodiment anaperture array 6A. The aperture array 6A may block part of the beam andmay allow a plurality of subbeams 20 to pass through the aperture array6A. The aperture array preferably comprises a plate havingthrough-holes. Thus, a plurality of parallel electron subbeams 20 may beproduced.

A second aperture array 6B may create a number of beamlets 7 from eachsubbeam. Beamlets are also being referred to as e-beams. The system maygenerate a large number of beamlets 7, preferably about 10,000 to1,000,000 beamlets, although it is of course possible to use more orless beamlets. Note that other known methods may also be used togenerate collimated beamlets. This allows the manipulation of thesubbeams, which turns out to be beneficial for the system operation,particularly when increasing the number of beamlets to 5,000 or more.Such manipulation is for instance carried out by a condenser lens, acollimator, or lens structure converging the subbeams to an opticalaxis, for instance in the plane of the projection lens.

A condenser lens array 21 (or a set of condenser lens arrays) may beincluded behind the subbeam creating aperture array 6A, for focusing thesubbeams 20 towards a corresponding opening in the beam stop array 10. Asecond aperture array 6B may generate beamlets 7 from the subbeams 20.Beamlet creating aperture array 6B is preferably included in combinationwith the beamlet blanker array 9. For instance, both may be assembledtogether so as to form a subassembly. In FIG. 9, the aperture array 6Bproduces three beamlets 7 from each subbeam 20, which strike the beamstop array 10 at a corresponding opening so that the three beamlets areprojected onto the target by the projection lens system in the endmodule 22. In practice a much larger number of beamlets may be producedby aperture array 6B for each projection lens system in end module 22.In one embodiment, 49 beamlets (arranged in a 7×7 array) may begenerated from each subbeam and are directed through a single projectionlens system, although the number of beamlets per subbeam may beincreased to 200 or more.

Generating the beamlets 7 stepwise from the beam 4 through anintermediate stage of subbeams 20 has the advantage that major opticaloperations may be carried out with a relatively limited number ofsubbeams 20 and at a position relatively remote from the target. Onesuch operation is the convergence of the subbeams to a pointcorresponding to one of the projection lens systems. Preferably thedistance between the operation and the convergence point is larger thanthe distance between the convergence point and the target. Mostsuitably, use is made of electrostatic projection lenses in combinationherewith. This convergence operation enables the system to meetrequirements of reduced spot size, increased current and reduced pointspread, so as to do reliable charged particle beam lithography atadvanced nodes, particularly at nodes with a critical dimension of lessthan 90 nm.

The beamlets 7 may next pass through an array of modulators 9. Thisarray of modulators 9 may comprise a beamlet blanker array having aplurality of blankers, which are each capable of deflecting one or moreof the electron beamlets 7. The blankers may more specifically beelectrostatic deflectors provided with a first and a second electrode,the second electrode being a ground or common electrode. The beamletblanker array 9 constitutes with beam stop array 10 a modulating device.On the basis of beamlet control data, the modulating means 8 may add apattern to the electron beamlets 7. The pattern may be projected ontothe target 24 by means of components present within an end module 22.

In this embodiment, the beam stop array 10 comprises an array ofapertures for allowing beamlets to pass through. The beam stop array, inits basic form, may comprise a substrate provided with through-holes,typically round holes although other shapes may also be used. In oneembodiment, the substrate of the beam stop array 8 may be formed from asilicon wafer with a regularly spaced array of through-holes, and may becoated with a surface layer of a metal to prevent surface charging. Inone embodiment, the metal may be of a type that does not form anative-oxide skin, such as CrMo.

In one embodiment, the passages of the beam stop array 10 may be alignedwith the holes in the beamlet blanker array 9. The beamlet blanker array9 and the beamlet stop array 10 typically operate together to block orlet pass the beamlets 7. If beamlet blanker array 9 deflects a beamlet,it will not pass through the corresponding aperture in beamlet stoparray 10, but instead will be blocked by the substrate of beamlet blockarray 10. But if beamlet blanker array 9 does not deflect a beamlet,then it will pass through the corresponding apertures in beamlet stoparray 10 and will then be projected as a spot on a target surface 13 ofthe target 24.

The lithography machine 1 may furthermore comprise a data path forsupplying beamlet control data, e.g. in the form of pattern bitmap data2009, to the beamlet blanker array 9. The beamlet control data may betransmitted using optical fibers. Modulated light beams from eachoptical fiber end may be projected on a light sensitive element on thebeamlet blanker array 9. Each light beam may hold a part of the patterndata for controlling one or more modulators coupled to the lightsensitive element.

Subsequently, the electron beamlets 7 may enter the end module.Hereinafter, the term ‘beamlet’ refers to a modulated beamlet. Such amodulated beamlet effectively comprises time-wise sequential portions.Some of these sequential portions may have a lower intensity andpreferably have zero intensity—i.e. portions stopped at the beam stop.Some portions may have zero intensity in order to allow positioning ofthe beamlet to a starting position for a subsequent scanning period.

The end module 22 is preferably constructed as an insertable,replaceable unit, which comprises various components. In thisembodiment, the end module may comprise a beam stop array 10, a scanningdeflector array 11, and a projection lens arrangement 12, although notall of these need be included in the end module and they may be arrangeddifferently.

After passing the beamlet stop array 10, the modulated beamlets 7 maypass through a scanning deflector array 11 that provides for deflectionof each beamlet 7 in the X- and/or Y-direction, substantiallyperpendicular to the direction of the undeflected beamlets 7. In thisembodiment, the deflector array 11 may be a scanning electrostaticdeflector enabling the application of relatively small driving voltages.

Next, the beamlets may pass through projection lens arrangement 12 andmay be projected onto a target surface 24 of a target, typically awafer, in a target plane. For lithography applications, the targetusually comprises a wafer provided with a charged-particle sensitivelayer or resist layer. The projection lens arrangement 12 may focus thebeamlet, for example resulting in a geometric spot size of about 10 to30 nanometers in diameter. The projection lens arrangement 12 in such adesign for example provides a demagnification of about 100 to 500 times.In this preferred embodiment, the projection lens arrangement 12 isadvantageously located close to the target surface.

In some embodiments, a beam protector may be located between the targetsurface 24 and the focusing projection lens arrangement 12. The beamprotector may be a foil or a plate, provided with needed apertures, forabsorbing the resist particles released from the wafer before they canreach any of the sensitive elements in the lithography machine.Alternatively or additionally, the scanning deflection array 9 may beprovided between the projection lens arrangement 12 and the targetsurface 24.

Roughly speaking, the projection lens arrangement 12 focuses thebeamlets 7 to the target surface 24. Therewith, it further ensures thatthe spot size of a single pixel is correct. The scanning deflector 11may deflect the beamlets 7 over the target surface 24. Therewith, itneeds to ensure that the position of a pixel on the target surface 24 iscorrect on a microscale. Particularly, the operation of the scanningdeflector 11 needs to ensure that a pixel fits well into a grid ofpixels which ultimately constitutes the pattern on the target surface24. It will be understood that the macroscale positioning of the pixelon the target surface is suitably enabled by a wafer positioning systempresent below the target 24.

Such high-quality projection may be relevant to obtain a lithographymachine that provides a reproducible result. Commonly, the targetsurface 24 comprises a resist film on top of a substrate. Portions ofthe resist film may be chemically modified by application of thebeamlets of charged particles, i.e. electrons. As a result thereof, theirradiated portion of the film may be more or less soluble in adeveloper, resulting in a resist pattern on a wafer. The resist patternon the wafer may subsequently be transferred to an underlying layer,i.e. by implementation, etching and/or deposition steps as known in theart of semiconductor manufacturing. Evidently, if the irradiation is notuniform, the resist may not be developed in a uniform manner, leading tomistakes in the pattern. Moreover, many of such lithography machinesmake use of a plurality of beamlets. No difference in irradiation oughtto result from deflection steps.

FIG. 10 shows a conceptual diagram of an exemplary charged particlelithography system 1A, divided into three high level sub-systems: awafer positioning system 25, an electron optical column 20, and datapath 30. The wafer positioning system 25 moves the wafer 24 under theelectron optical column 20 in the x-direction. The wafer position system25 may be provided with synchronization signals from the data pathsub-system 30 to align the wafer with the electron beamlets generated bythe electron-optical column 20. The electron-optical column 20 mayinclude the charged particle multi-beamlet lithography machine 1 asshown in FIG. 9. Switching of the beamlet blanker array 9 may also becontrolled via the data path sub-system 30, using pattern bitmap data2009. The data path sub-system 30 may be implemented in accordance withFIG. 3.

As shown in the above examples, a maskless pattern writer may apply araster scan to the wafer under control of pattern bitmap data.Alternatively, a maskless pattern writer may apply a vector scan to thewafer. A vector scan typically differs from a raster scan in that itdoes no sequentially go through every location of the wafer; instead, itfinishes exposing one local area and flies to the next. With vectorscanning a beam settling time is typically needed before the subsequentexposure resumes. This settling time is typically not needed for theraster scan. The pattern bitmap data and the control data for vectorscanning may generally be referred to as beamlet control data.

The invention claimed is:
 1. A computer-implemented method for generating a feature data set, the method comprising: generating the feature data set by defining features selectable for individualizing electronic devices, selecting a plurality of subsets of the features of the feature data set, the plurality of subsets having a different selection of features for different subsets of the electronic devices, and generating, based on the selected plurality of subsets of the features, control data for exposing a pattern having the selected plurality of subsets of the features corresponding to the subsets of the electronic devices onto a wafer.
 2. The method of claim 1, wherein the feature data set is generated by defining a plurality of features selectable for complementing structures defined in a design layout data defining structures applicable for all the electronic devices to be manufactured from the wafer.
 3. The method of claim 1, wherein the feature data set is generated as a plurality of data files, wherein each data file comprises a subset among the plurality of subsets of the features applicable to one of the different subsets of the electronic devices.
 4. The method of claim 1, wherein the feature data set is generated as a data file, wherein the data file comprises the plurality of subsets of the features, wherein each subset of the features is applicable to one of the different subsets of the electronic devices.
 5. The method of claim 1, further comprising generating selection data by defining a selection of the features of the feature data set for individualizing the electronic devices, the selection data defining a different selection of the features for different subsets of the electronic devices to be manufactured from the wafer.
 6. The method of claim 5, further comprising generating feature meta data by specifying a location where the features from the feature data set are to be created for individualizing the electronic devices.
 7. A data processing system comprising a processor configured to perform a computer-implemented method for generating a feature data set, the method comprising: generating the feature data set by defining features selectable for individualizing electronic devices, selecting a plurality of subsets of the features defined by the feature data set, the plurality of subsets having a different selection of features for different subsets of electronic devices, and generating, based on the selected plurality of subsets of the features, control data for exposing a pattern having the selected plurality of subsets of features onto a wafer. 